The present invention relates to the field of computer system bus architectures. More particularly, the present invention relates to a smart retry system that reduces wasteful retry bus transactions between master devices and slave devices.
The bus architecture of a computer system substantially influences the manner in which information is communicated between components of a computer system. In a typical computer system, one or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements. Typically the bus consists of several xe2x80x9clinesxe2x80x9d of electrically conductive material. The bus permits electrical signals representing data and control instructions to be readily transmitted between different components. The speed at which the components interact with each other over the bus has a substantial impact on the performance and utility of the computer system.
Ordinarily, the faster a computer system component responds to the CPU, the more useful the computer system is to the user. Much of a computer system""s functionality and utility is realized through the use of components referred to as peripheral devices. Frequently, the speed at which peripheral devices interact with the rest of the computer system is critical. For many peripheral devices, such as graphics adapters, full motion video adapters, small computer system interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. For example, the speed at which a graphics adapter can communicate its responses is a major factor in a computer system""s usefulness as an entertainment device. Or, for example, the speed at which video files can be retrieved from a hard drive and played by the graphics adapter has a significant impact on the computer system""s usefulness as a training aid. Hence, the rate at which data can be transferred among various peripheral devices often determines whether the computer system is suited for a particular purpose. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate.
In order to increase the capability of computer systems, the electronics industry has engaged in activities to develop several types of progressively faster bus architectures. Recently, PCI (peripheral component interconnect) bus architecture was developed to provide a high speed, low latency bus architecture from which a large variety of computer systems could be developed. The PCI bus architecture has become one of the most widely used and supported bus architectures in the industry.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, both coupled to a host PCI bridge arbiter 106 (hereafter PCI arbiter 106). CPU 102 is coupled to PCI arbiter 106 through a CPU local bus 108. Main memory 104 is coupled to PCI arbiter 106 by memory bus 110. The PCI bus 112 is coupled to arbiter 106 and to each of the PCI compliant devices or xe2x80x9cagentsxe2x80x9d 114, 116, 118, 120, 122, 124 respectively. PCI agents 114, 116, 118, 120, 122, 124 (hereafter referred to collectively as PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive information and signals. PCI bus 112 is comprised of functional signal lines and data lines; for example, interface control lines, address/data lines, error signal lines, and the like. PCI agents 114-124 follow a definitive set of protocols and rules designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112. PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specificationxe2x80x94Revision 2.1).
The industry standard PCI specification dictates that when one of the PCI agents 114-124 requires the use of PCI bus 112 to transmit or receive data, the PCI agent requests PCI bus 112 xe2x80x9cownershipxe2x80x9d from PCI arbiter 106. The PCI agent requesting ownership is referred to as a PCI initiator agent, or master device. The term master device is generically used in bus systems, including systems other than PCI. Each of the PCI agents 114-124 may independently act as a PCI initiator agent and request PCI bus ownership. Thus, at any given time several of the PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, PCI arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent will be granted PCI bus ownership. In accordance with PCI architecture standards, only one data transaction can take place on a PCI bus at any given time. Therefore, the arbiter only grants PCI bus access to one PCI initiator agent at any given time and no other PCI initiator agents may conduct a transaction on the PCI bus at the same time. The PCI agent the PCI initiator agent is attempting to communicate with is referred to as a PCI target agent (e.g., main memory 104) or slave device. The term slave device is generically used in bus systems, including systems other than PCI. It is only after the PCI initiator agent has been granted PCI bus ownership that the PCI initiator agent attempts to access the PCI target agent and initiate a transaction (e.g., data transfer).
The PCI initiator agent begins the transaction by identifying or addressing the PCI target agent during the address phase of the transaction. Once the PCI target agent senses it is being addressed, continuation of a transaction is dependent on the PCI target agent. If the PCI target agent indicates it is ready the transaction continues. When the PCI initiator agent has completed its transaction, it relinquishes ownership of the PCI bus 112, allowing PCI arbiter 106 to reassign PCI bus 112 to another PCI initiator agent. However, if the PCI target agent is not ready for the transaction to continue, it signals the PCI initiator agent to retry. By signaling a retry, the PCI target agent is instructing the PCI initiator agent to stop the current transaction and try to complete it later.
The PCI target agent may issue a retry for many reasons. For example, in computer systems with one or more PCI agents which are slower than others (as is often the case), slower PCI target agents issue retry signals to avoid PCI bus xe2x80x9cmonopolizationxe2x80x9d by particular PCI agents. The industry standard PCI specification dictates that a PCI initiator agent should issue a retry if its latency will exceed 16 PCI clock cycles. If the industry standard PCI specification did not require slow PCI target agents to issue retry signals under certain conditions, transactions with the slowest PCI agent could occupy the PCI bus 112 for long periods of time and effectively xe2x80x9cmonopolizexe2x80x9d the PCI bus. For example, PCI agent 118 is an ISA (industry standard architecture) bus bridge and is typically much slower than the other PCI agents. In addition, other peripheral devices coupled to the ISA bus can be slower still, resulting in PCI agent 118 typically having a very slow access time from the viewpoint of a PCI initiator agent (e.g. PCI agent 122). This relative slowness potentially causes a PCI initiator agent (e.g., PCI agent 122) to wait a relatively long period of time between accessing the PCI bus 112 and beginning the data transaction phase, tying up PCI bus 112 in the process.
It should be noted that there may be other reasons a PCI target agent may have a slow access time. For example, the PCI target agent may be busy with some internal activity and is unable to service the access at that time, or the access would generate some sort of internal conflict (e.g., with data ordering or coherency). Accordingly, where a PCI target agent xe2x80x9cknowsxe2x80x9d it will be slow completing a transaction, it may issue a retry in order to free up the PCI bus for other PCI initiator agents. In accordance with industry standard PCI specifications, when a PCI target agent issues a retry signal the PCI initiator agent must terminate its access of the PCI bus and retry later.
In addition to providing order to the communication process, the industry standard PCI specifications typically try to provide for protocols that enhance the computer system""s performance. Given the general proposition that the faster information and signals are communicated, the better the performance of a computer system, most PCI initiator agents are designed to complete their access in the minimum time possible. Accordingly, when the PCI initiator agent receives a retry from the PCI target agent, the PCI initiator agent deasserts the request for the minimum time allowed by PCI standards (i.e., two PCI clocks) and then retries the access. This process is repeated until the access is successful, that is, until the data is transferred between the PCI initiator agent and PCI target agent. However, the PCI initiator agent""s quickly repeated retry attempts often occur before the PCI target agent has had sufficient time to clear the condition that caused it to issue the retry in the first place. Hence, the PCI target agent issues repeated retry signals.
FIG. 2 shows a diagram of a prior art retry access process 200. Process 200 depicts a typical access sequence when a PCI target agent is not ready for a transaction and issues a retry to the PCI initiator agent. For example, the PCI initiator agent may have a high data transfer rate (e.g., PCI agent 122) and the PCI target agent is a device that has a slow data transfer rate and a high latency (e.g., PCI agent 118). On the left side of process 200, the PCI initiator agent attempts to access the PCI target agent, shown as the initial access 201. The initial access is comprised of a normal PCI arbitration process and the usual initial steps of a PCI transaction. For example, the PCI initiator agent requests the PCI bus, the arbiter eventually decides (usually in accordance with a system specific algorithm) to grant the PCI initiator agent access to the PCI bus, the PCI initiator agent addresses the PCI target agent and identifies the type of transaction. The PCI target agent is not ready and issues a retry 205. This forces the PCI initiator agent to relinquish the PCI bus (i.e., PCI bus 112) for other uses. The PCI initiator agent subsequently arbitrates for and acquires the PCI bus for a second try 202. The PCI target agent is still not ready, and thus, issues retry 206, forcing the PCI initiator agent to again relinquish the PCI bus. In accordance with PCI protocol, the PCI initiator agent continually attempts to execute its data transaction (as shown by third try 203 through xe2x80x9cNxe2x80x9d th try 204) and is forced to retry (207 through 208 respectively) until the PCI target agent is ready and the transaction is completed 209.
During each try (202, 203 and 204) the PCI bus is unnecessarily tied up by the PCI initiator agent repeatedly addressing the PCI target agent and trying to transfer data when the PCI target agent is not ready. As indicated in legend 210, the space occupied by the hexagonal figures in process 200 represents occupied PCI bus access time that is essentially wasted because the PCI target agent is not ready. That is, no other PCI agents can access the PCI bus during the PCI initiator agent""s repeated accesses of the PCI bus. This slows down the speed at which a computer system can complete tasks. Thus, when a PCI initiator agent repeatedly attempts to access a PCI target in response to retry signals, and the PCI target agent is not ready, a computer system""s performance and functionality is usually diminished.
Thus, what is required is a method and system which reduces wasted retry attempts. The required method and system should enhance the performance of a computer system by increasing the data transfer rates and bandwidth of computer system buses. What is further desired is a method and system to coordinate the timing of bus access retry attempts to optimize the probably of successfully completing the transaction and reducing wasted bus access time. The present invention provides a novel solution to the above requirements.
The present invention is a novel smart retry method and system which reduces wasted bus time associated with futile retry attempts by master devices. By reducing futile and wasteful grants of bus time the invention significantly increases available bus data transfer bandwidth. The present invention synchronizes the timing of bus access retry attempts to instances that optimize the probability of successfully completing the transaction, thus reducing wasted bus access time.
In one embodiment, the present invention comprises a smart retry system for a device in a computer system. The smart retry system of the present invention includes a master device, a slave device, an arbiter, and a smart retry logic component, all adapted to be coupled to a bus. The bus permits devices coupled to the bus to communicate with the arbiter and other devices coupled to the bus. The smart retry logic component of the present invention prevents a master device from accessing the bus for the purpose of attempting a retry transaction, until after the slave device that issued the retry is ready.
Another embodiment comprises a smart retry system implemented in a PCI (peripheral component interconnect) system. When signaled by a PCI target agent not to grant a particular PCI initiator agent access to a PCI bus, a PCI arbiter masks the PCI initiator agent""s requests for PCI bus access. Thus, the smart retry system minimizes the time a PCI initiator agent ties up the PCI bus with futile retry attempts to access a PCI target agent.